1. Field of the Invention
The present invention relates to the field of computer systems. More particularly, the present invention relates to a flexible memory hierarchy including a dedicated memory transfer bus, controlled by an operating system, for exchanging data between different memory types.
2. Description of Related Art
It is common knowledge that a conventional computer system comprises a central processing unit ("CPU") and a memory system. Generally, during read cycles, the CPU fetches data of an arbitrary bit length (e.g., blocks) from physical (or real memory) address locations within the memory system. Since the CPU normally operates at a greater speed than the memory system, the overall performance of the computer system is significantly influenced by the rate at which data may be accessed from memory ("bandwidth") and the time delay experienced by the CPU before it obtains access to such data ("memory latency").
Typically, in order to achieve a requisite bandwidth and to provide a requisite amount of addressable memory space, the memory system is arranged according to a strict, inflexible hierarchy. This hierarchy typically features multiple memory types, each of these memory types having a predetermined, unique physical (or real memory) address space. Examples of these memory types include low-speed main memory (e.g., dynamic random access memory "DRAM", video random access memory "VRAM", etc.), high-speed cache memory (typically being a multiple-level cache having a bandwidth greater than the low-speed memory), and remote memory (disk storage devices, main memory of another computer system, etc.) being "slower" (i.e., having a lesser bandwidth) than both cache and main memory. Typically, "high-speed" memory has a bandwidth of approximately 83 MHz or an access time of approximately 12 nanoseconds while low speed memory and remotely located memories have a bandwidth of approximately 20 MHz or an access time of approximately 50 nanoseconds and 3.3 KHz or an access time of approximately 300 microseconds, respectively.
According to this inflexible memory hierarchy, the most-recently-used data is stored in the high-speed cache memory and lesser used data is stored in the other slower memory types. Although the above-described inflexible hierarchy provides a cost-effective approach in achieving a requisite bandwidth for a given memory space, it possesses a number of disadvantages.
One disadvantage associated with the conventional, inflexible memory hierarchy is that pre-configured hardware (e.g., a CPU controller), employed within the computer system, is utilized as an oracle to predict what data is likely to be accessed in the near future and writes that data into both cache memory and main memory. However, this method of prediction may not be varied by the computer operator nor by the operating system of the computer system, both of which would be more accurate predictors than the CPU controller. In fact, the computer operator would have knowledge as to which data will be more frequently accessed by an application program.
Another disadvantage associated with the conventional, inflexible memory hierarchy is that it is quite susceptible to cache collisions. Such susceptibility is primarily due to the fact that certain cache lines are re-used more frequently than other cache lines according to conventional cache and operating system storage techniques well-known in the art.
Yet another disadvantage is that the conventional memory hierarchy imposes constraints on the size of a data transfer, usually limited to a single cache line or another predetermined data structure of equivalent size. These constraints are imposed because data transfers greater than a cache line would consume greater memory bus bandwidth, increase memory latency and reduce CPU bandwidth.